Memory devices are ubiquitous in computing devices to store data and code for a processor to execute operations and accomplish the function of the computing devices. Even as the demand for computing devices grows, there is a trend towards smaller computing devices that operate on less power, especially in mobile devices. Mobile computing devices have increased in computational performance, they have included more and more storage and memory to meet the needs of the programming and computing performed on the devices. In mobile computing devices, controlling power consumption is a key design focus. Memory devices and memory subsystems consume a significant amount of total power consumption in low power and other mobile devices.
Current memory subsystems can control memory system power consumption by eliminating on-die termination (ODT) during Write operations. While the signal quality might be degraded due to a lack of ODT, such a tradeoff can be tolerated if the distance between memory devices is small enough that the signal reflections do not significantly impact the desired signal. Such assumptions do not always hold in current systems. While some packaging solutions exist to increase the memory density in mobile device while maintaining distances between devices small, such solutions tend to be more costly and non-standard. More standard packaging solutions are less costly, but increase the distances between memory devices on the memory bus as densities increase. Thus, the distances between memory devices can cause signal degradation due to signal reflections without ODT in standard packaging solutions. Current ODT solutions use ODT pins, which use increases manufacturing cost and consumes more real estate as it increases pin count. Some ODT solutions exist that do not use separate ODT pins, but such solutions are limited to providing termination in one rank, such as by hard-coding the termination scheme. Single-rank ODT is not a sufficient solution for multi-rank memory systems.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.